Borderless vias with CVD barrier layer
US6159851A · kind A · utility
23Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Apr 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H.sub.2 /N.sub.2 plasma to lower its resistivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.