John A. Iacoponi
53Patents
17h-index
42Co-inventors
84Inventor score
Filing activity: Feb 24, 1995 → Aug 27, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6468889B1 | Backside contact for integrated circuit and method of forming same | Electricity | 73 | Expired |
| US6103085A | Electroplating uniformity by diffuser design | Chemistry; Metallurgy | 72 | Expired |
| US5918149A | Deposition of a conductor in a via hole or trench | Electricity | 70 | Expired |
| US6228754A | Method for forming semiconductor seed layers by inert gas sputter etching | Electricity | 51 | Expired |
| US5545592A | Nitrogen treatment for metal-silicide contact | Electricity | 34 | Expired |
| US6239021A | Dual barrier and conductor deposition in a dual damascene process for semiconductors | Emerging Cross-Sectional Technologies | 32 | Expired |
| US6232230A | Semiconductor interconnect interface processing by high temperature deposition | Electricity | 31 | Expired |
| US6117770A | Method for implanting semiconductor conductive layers | Electricity | 31 | Expired |
| US6048790A | Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient | Electricity | 27 | Expired |
| US6261946A | Method for forming semiconductor seed layers by high bias deposition | Electricity | 27 | Expired |
| US6159851A | Borderless vias with CVD barrier layer | Electricity | 23 | Expired |
| US6187670A | Multi-stage method for forming optimized semiconductor seed layers | Electricity | 23 | Expired |
| US7557035B1 | Method of forming semiconductor devices by microwave curing of low-k dielectric films | Electricity | 22 | Active |
| US6100181A | Low dielectric constant coating of conductive material in a damascene process for semiconductors | Electricity | 19 | Expired |
| US6362526B1 | Alloy barrier layers for semiconductors | Emerging Cross-Sectional Technologies | 19 | Expired |
| US6555479B1 | Method for forming openings for conductive interconnects | Electricity | 18 | Expired |
| US6147404A | Dual barrier and conductor deposition in a dual damascene process for semiconductors | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6649533B1 | Method and apparatus for forming an under bump metallurgy layer | Electricity | 16 | Expired |
| US6340633B1 | Method for ramped current density plating of semiconductor vias and trenches | Electricity | 16 | Expired |
| US6080669A | Semiconductor interconnect interface processing by high pressure deposition | Electricity | 12 | Expired |
| US6218078A | Creation of an etch hardmask by spin-on technique | Electricity | 11 | Expired |
| US6489240B1 | Method for forming copper interconnects | Electricity | 10 | Expired |
| US6809032B1 | Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques | Electricity | 10 | Expired |
| US6166427A | Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application | Electricity | 10 | Expired |
| US5969425A | Borderless vias with CVD barrier layer | Electricity | 10 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.