Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths
US6160316A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Mar 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a multi-level interconnect in which capacitive coupling between laterally adjacent conductors employed by an integrated circuit is reduced. According to an embodiment, a conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the conductor. Select portions of the conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the conductor. An interlevel dielectric is deposited to a level above the masking structure such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the conductor, and the interlevel dielectric is planarized to a level spaced above an upper surface of the masking structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.