Method and apparatus for testing SRAM memory cells
US6161204A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the, test mode signal is inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.