Method of fabricating a data-storage capacitor for a dynamic random-access memory device
US6162670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method is provided for fabricating a data-storage capacitor for a DRAM device, which can help increase the capacitance of the resulted capacitor. By this method, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially formed over the substrate. An opening is formed in the third insulating layer, and a contact hole is formed to expose a source/drain region in the substrate. Subsequently, a conductive layer is formed over the third insulating layer, which is electrically connected to the exposed source/drain region. Next, a fourth insulating layer is formed over the conductive layer. A surface part of the third and fourth insulating layers is removed until reaching a predefined depth to allow an upper part of the conductive layer to be exposed. Next, conductive sidewall spacers are formed on the exposed part of the conductive layer to increase the surface area of the conductive layer. The combined structure of the conductive layer and the conductive sidewall spacers serves as a bottom electrode. Subsequently, a dielectric layer is formed over the bottom electrode, and then a top electrode is formed over the dielectric layer. This completes…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.