Method for forming metalization for inter-layer connections
US6162724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an improved method for forming metalization layers for inter-layer connections including the steps of first providing a substrate, then depositing a metal layer on the substrate, then depositing a dielectric layer overlying the metal layer, etching away an opening in the dielectric layer to expose at least partially the metal layer, and etching an opening in the metal layer by using the dielectric layer as a mask to at least partially expose the underlying substrate. The method may optionally includes the step of blanket depositing a thin oxide layer and then an inter-level dielectric layer on top of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.