Method for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAM
US6162732A · kind A · utility
1Cited by
7References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 7, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Apr 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
Abstract
A method of forming hemispherical grain (HSG) silicon is disclosed. The method comprises the steps of: forming a doped amorphous silicon layer on a substrate; seeding and annealing the amorphous silicon layer until HSG silicon is formed; enlarging the HSG silicon grains during the annealing stage; and performing a chemical dry etch on the HSG silicon to remove an undoped silicon layer from the surface of the HSG silicon.
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