Method of fabricating a self aligned contact for a capacitor over bitline, (COB), memory cell
US6163047A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 12, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Jul 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A process for fabricating a capacitor over bitline, DRAM device, using a self-aligned contact opening, through, and between the bitline structures, and featuring the formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, has been developed. The self-aligned contact opening, located through the bitline structures, allows an increase in DRAM cell density to be achieved. The formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, in a silicon oxide layer, allows silicon oxide to be used as the spacer material, thus resulting in capacitance decrease when compared to counterparts fabricated using silicon nitride spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.