Method and apparatus for controlling timing of digital components
US6166576A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Sep 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for controlling a timing of a digital component having an impedance-input terminal. The method includes determining an impedance level present at the impedance-input terminal, and delaying the timing of the digital component based on the impedance level. The present invention also provides a digital component and a system, where the digital component includes an impedance-input terminal and an impedance matching circuit that is capable of determining an impedance level present at the impedance-input terminal. The digital component also includes a delay circuit that is capable of delaying a timing of the digital component based on the impedance level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.