Multiple equilibration circuits for a single bit line
US6166976A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.