Method fabricating metal interconnected structure
US6169028A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.