Metallization process and method
US6169030A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1998 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Jan 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power. Even more preferably, the plasma power is varied from a first discrete low plasma power to a second discrete low plasma power to a third discrete high plasma power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.