Semiconductor chip assembly
US6169328A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion ("CTE") and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip. The encapsulant encases the conductive leads electrically connecting the terminals to chip contacts on a face surface of the chip. The lower CTE of the encapsulant controls the flexing of the conductive leads so that the leads do not prematurely fatigue and becom…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.