Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6169329A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1996 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Apr 2, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making a semiconductor device and the resulting device having standardized die-to-substrate bonding locations are herein disclosed. The semiconductor die provides a standardized ball grid or other array of a particular size, pitch and pattern such that as the size, configuration or bond pad arrangement of the die changes, a standard substrate (the term including leadframes) having a similarly standardized array of terminals or trace ends can be employed to form a semiconductor device. It is also contemplated that dies having markedly different circuitry but a common array pattern may be employed with the same substrate or other carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.