Trace based instruction caching
US6170038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.