Method and system for floorplanning a circuit design at a high level of abstraction
US6170080A · kind A · utility
42Cited by
16References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.