Method of fabricating a dynamic random access memory capacitor
US6171924A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Oct 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method of fabricating a capacitor on a substrate. The method includes sequentially forming a first dielectric layer and an etching barrier layer on the substrate, the etching barrier layer and the first dielectric layer having an opening formed therein. A conductive layer is formed on the etching barrier layer and fills the opening. The conductive layer is patterned to form a raised region on the conductive layer. Isolation spacers and conductive spacers are alternately formed on sidewalls of the raised region. The isolation spacers and the conductive spacers are concentrically layered. The isolation spacers are used as masks to remove the conductive spacers and a portion of the patterned conductive layer. The etching barrier layer is used as an etch stop layer. The isolation spacers and a portion of the patterned conductive layer are removed. The remaining patterned conductive layer forms a storage electrode of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.