Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
US6174743A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During deposition, silane flow rates are regulating and reducing to less than sixty standard cubic centimeters per minute, thereby reducing the incidence of stress-induced voiding in the underlying interconnect lines. During deposition adjustments are made in deposition temperature and process pressure to control the characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO.sub.2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.