Method of forming trench isolation region for semiconductor device
US6174785A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Jun 18, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer shape is transferred into a semiconductor substrate during an etching process to define the profile of the trench, resulting in a trench with substantially rounded upper and lower corners in the substrate. An oxide filler material is deposited in the trench and over the substrate to form a covering layer. The covering layer is then polished back to form a filled trench region which electrically isolates active areas in the substrate. The polishing step can be performed by a blanket dry etching procedure, or by a combination of chemical/mechanical planarization and wet etching. The rounded shape of the trench improves the electrical characteristics of the trench such that current leakage is decreased, and also provides a more optimized trench profile for filling the trench with the filler material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.