Precharging mechanism and method for NAND-based flash memory devices
US6175523A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a mechanism for precharging the bitline line of each page buffer prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging mechanism increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The precharging mechanism includes a first transistor connected between a power supply and the bitline that is operational during the precharge cycle and causes the bitline to charge to the predetermined voltage. The precharging mechanism also includes a second transistor connected between a latch disposed in the page buffer and ground. The second transistor grounds the latch prior to the start of the evaluation cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.