Separate output power supply to reduce output noise for a simultaneous operation
US6178129A · kind A · utility
13Cited by
7References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device (100) provides for simultaneous read and write operations in two banks (194, 196) of flash memory cells. A plurality of output circuits (182) switch large amounts of current during reading of stored data. To reduce noise in read circuitry (174) and write circuitry (142), a separate power supply bus (204) and ground bus (208) is provided for the output circuits. The power supply bus is independent of the power supply bus which serves the internal circuitry, such as the read circuitry and the write circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.