Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode
US6178467A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1998 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Jul 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for transferring data between a processor and a device residing at a non-cacheable address. The method includes the steps of asserting the non-cacheable address onto an address bus, asserting a first signal indicating that the processor has data ready for burst mode transfer between the processor and a device residing at the non-cacheable address, asserting a second signal indicating that the device is ready for the burst mode transfer, and performing a burst mode transfer of a plurality of bytes between the processor and the non-cacheable address. The method of the invention provides both sequential and non-sequential burst transfer modes. The system of the invention provides a processor, a device, bus control logic, and non-cacheable address logic. The bus control logic and the non-cacheable address logic are configured to implement new semantic meanings for the CACHE# and KEN# signals that eliminate the distinction between cacheable and non-cacheable address space for purposes of allowing burst mode transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.