FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements
US6180470A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1996 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Dec 19, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/925
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.