Process of fabricating planar and densely patterned silicon-on-insulator structure

US6180486A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Effendi Leobandung · Stormville, US
• Devendra K. Sadana · Pleasantville, US
• Dominic J. Schepis · Wappingers Falls, US
• Ghavam G. Shahidi · Pound Ridge, US

Key dates

• Filing date: Feb 16, 1999
• Grant date: Jan 30, 2001
• Expiry date: Feb 16, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76278
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.