Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device
US6181154A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a die having a semiconductor memory circuit formed thereon and a plurality of pads at the periphery of the die that are electrically coupled to the circuit. Electrically conductive leads have a pin end for external coupling, and a free end electrically connected by bond wires to certain pads on the die. An encapsulating material such as epoxy encapsulates the die, bond wires and free ends of the leads to form a packaged chip. A superfluous lead such as an address lead unused during testing, redundant voltage supply lead or non-connected lead is coupled, by means of a bond wire, to a pad that, in turn, is coupled through a switching transistor to a common cell plate or DVC2 node for all storage capacitors in the memory circuit. External power can thereby be provided to the DVC2 node to simultaneously apply a high voltage to this node of all capacitors during stress testing of the chip. The arrangement allows for efficient testing for dielectric defects in the capacitors while the die is in packaged chip form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.