Ray Beffa
29Patents
15h-index
9Co-inventors
70Inventor score
Filing activity: Sep 19, 1995 → Apr 7, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6032264A | Apparatus and method implementing repairs on a memory device | Physics | 83 | Expired |
| US5910921A | Self-test of a memory device | Physics | 68 | Expired |
| US5867505A | Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit | Physics | 59 | Expired |
| US5982682A | Self-test circuit for memory integrated circuits | Physics | 50 | Expired |
| US5657284A | Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices | Physics | 48 | Expired |
| US6233185A | Wafer level burn-in of memory integrated circuits | Physics | 47 | Expired |
| US6058056A | Data compression circuit and method for testing memory devices | Physics | 39 | Expired |
| US5754486A | Self-test circuit for memory integrated circuits | Physics | 38 | Expired |
| US6119251A | Self-test of a memory device | Physics | 27 | Expired |
| US5852581A | Method of stress testing memory integrated circuits | Physics | 24 | Expired |
| US6625073B1 | Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices | Physics | 21 | Expired |
| US5898629A | System for stressing a memory integrated circuit die | Physics | 20 | Expired |
| US6128756A | System for optimizing the testing and repair time of a defective integrated circuit | Physics | 19 | Expired |
| US6145092A | Apparatus and method implementing repairs on a memory device | Physics | 16 | Expired |
| US6181154A | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | Physics | 15 | Expired |
| US6094734A | Test arrangement for memory devices using a dynamic row for creating test data | Physics | 15 | Expired |
| US6003149A | Test method and apparatus for writing a memory array with a reduced number of cycles | Physics | 14 | Expired |
| US6079037A | Method and apparatus for detecting intercell defects in a memory device | Physics | 14 | Expired |
| US5966025A | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | Physics | 11 | Expired |
| US6477662B1 | Apparatus and method implementing repairs on a memory device | Physics | 10 | Expired |
| US6347386B1 | System for optimizing the testing and repair time of a defective integrated circuit | Physics | 10 | Expired |
| US5885846A | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | Physics | 10 | Expired |
| US5965902A | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | Physics | 8 | Expired |
| US7069484B2 | System for optimizing anti-fuse repair time using fuse id | Physics | 7 | Expired |
| US6622270B2 | System for optimizing anti-fuse repair time using fuse ID | Physics | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.