Global erase/program verification apparatus and method
US6181605A · kind A · utility
50Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Oct 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.