Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test
US6181616A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Circuits and systems for testing packet-based semiconductor devices by using facilitated test data packets are disclosed. Facilitated test data packets may be generated by conventional memory testers. The facilitated test data packets are realigned to another, different format automatically or by test mode circuitry located on circuit die, integrated circuit package, test interface, or semiconductor tester prior to testing the device under test. The data realignment may be synchronized by one or more timing signals. The circuits and systems described potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator (APG) on a per pin basis. Furthermore, the circuits and systems disclosed potentially reduce the number of packet words that have data generated from both an APG and vector memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.