System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
US6182195A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jul 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.