Method to elimate silicide cracking for nand type flash memory devices by implanting a polish rate improver into the second polysilicon layer and polishing it
US6184084A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer; forming a second polysilicon layer over the insulating layer by depositing an second polysilicon layer having a first thickness, and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF.sub.6 and SiH.sub.4 ; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.