Formation of controlled trench top isolation layers for vertical transistors

US6184091A · kind A · utility

Assignee

• Infineon Technologies North America Corp. · US

Inventors

• Ulrike Gruening · Wappingers Falls, US
• Jochen Beintner · Wappingers Falls, US
• Dirk Tobben · Fishkill, US
• Gill Yong Lee · San Jose, US
• Oswald Spindler · Vaterstetten, DE
• Zvonimir Gabric · Zorneding, DE

Key dates

• Filing date: Feb 1, 1999
• Grant date: Feb 6, 2001
• Expiry date: Feb 1, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.