Chip packaging
US6184573A · kind A · utility
163Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 13, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | May 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a chip package, particularly a dual-chip package, that is featured by directly connecting a lead frame to at least a chip included therein, and is specifically featured by directly connecting the inner leads of a lead frame to the bumps formed on at least two chips included therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.