Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
US6187645A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.