Minimization of line width variation in photolithography
US6187687A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Nov 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3081
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A practical photolithographic process for use in manufacturing isolation structures in semiconductor substrates at the 0.18 .mu.m scale uses an inorganic anti-reflective coating (ARC) layer, particularly silicon oxynitride, under a silicon nitride mask layer to minimize substrate reflectivity. The same ARC layer increases latitude in process conditions in photolithographic patterning of both a first mask layer and a second planarization mask level. The silicon oxynitride layer additionally reduces edge/corner stress in isolation structures, improving gate oxide integrity in the device of which the isolation structure forms a part. Furthermore, because silicon oxynitride and silicon nitride respond to the same process conditions, a silicon oxynitride ARC layer can be introduced without increasing process complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.