Marina V. Plat
68Patents
17h-index
46Co-inventors
80Inventor score
Filing activity: Oct 27, 1997 → Oct 27, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6773998B1 | Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning | Electricity | 157 | Expired |
| US6383952B1 | RELACS process to double the frequency or pitch of small feature formation | Electricity | 76 | Expired |
| US6818141B1 | Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines | Electricity | 60 | Expired |
| US6541360B1 | Bi-layer trim etch process to form integrated circuit gate structures | Emerging Cross-Sectional Technologies | 55 | Expired |
| US6534418B1 | Use of silicon containing imaging layer to define sub-resolution gate structures | Electricity | 51 | Expired |
| US6764949B2 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication | Electricity | 42 | Expired |
| US6867097B1 | Method of making a memory cell with polished insulator layer | Electricity | 29 | Expired |
| US6255125A | Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer | Electricity | 26 | Expired |
| US6417084B1 | T-gate formation using a modified conventional poly process | Electricity | 25 | Expired |
| US6900002B1 | Antireflective bi-layer hardmask including a densified amorphous carbon layer | Electricity | 25 | Expired |
| US6589711B1 | Dual inlaid process using a bilayer resist | Electricity | 23 | Expired |
| US6306769A | Use of dual patterning masks for printing holes of small dimensions | Physics | 21 | Expired |
| US6270929A | Damascene T-gate using a relacs flow | Electricity | 21 | Expired |
| US6057206A | Mark protection scheme with no masking | Electricity | 20 | Expired |
| US6358856B1 | Bright field image reversal for contact hole patterning | Electricity | 19 | Expired |
| US6262435A | Etch bias distribution across semiconductor wafer | Electricity | 18 | Expired |
| US7008832B1 | Damascene process for a T-shaped gate electrode | Electricity | 18 | Expired |
| US6326231A | Use of silicon oxynitride ARC for metal layers | Electricity | 17 | Expired |
| US6548423B1 | Multilayer anti-reflective coating process for integrated circuit fabrication | Electricity | 15 | Expired |
| US6403456B1 | T or T/Y gate formation using trim etch processing | Electricity | 15 | Expired |
| US6187687A | Minimization of line width variation in photolithography | Electricity | 15 | Expired |
| US6255202A | Damascene T-gate using a spacer flow | Electricity | 15 | Expired |
| US6864556B1 | CVD organic polymer film for advanced gate patterning | Electricity | 14 | Expired |
| US6222241A | Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer | Electricity | 13 | Expired |
| US6313019A | Y-gate formation using damascene processing | Emerging Cross-Sectional Technologies | 11 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.