Method and system for improving DRAM subsystem performance using burst refresh control
US6188627A · kind A · utility
6Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1999 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Aug 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than the entire DRAM array provides a lower latency than existing full DRAM burst techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.