Robert Allen Drehmel
30Patents
10h-index
44Co-inventors
75Inventor score
Filing activity: Apr 3, 1991 → Aug 14, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6526469B1 | Bus architecture employing varying width uni-directional command bus | Physics | 133 | Expired |
| US6513091B1 | Data routing using status-response signals | Physics | 103 | Expired |
| US6557069B1 | Processor-memory bus architecture for supporting multiple processors | Physics | 100 | Expired |
| US6247100A | Method and system for transmitting address commands in a multiprocessor system | Physics | 71 | Expired |
| US6895482B1 | Reordering and flushing commands in a computer memory subsystem | Physics | 53 | Expired |
| US7254663B2 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Physics | 33 | Expired |
| US6628662B1 | Method and system for multilevel arbitration in a non-blocking crossbar switch | Electricity | 30 | Expired |
| US6295591A | Method of upgrading and/or servicing memory without interrupting the operation of the system | Physics | 24 | Expired |
| US6505306B1 | Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization | Physics | 17 | Expired |
| US7461268B2 | E-fuses for storing security version data | Physics | 12 | Active |
| US5117384A | Method and apparatus for exponent adder | Physics | 10 | Expired |
| US7873773B2 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Physics | 7 | Active |
| US7234017B2 | Computer system architecture for a processor connected to a high speed bus transceiver | Physics | 7 | Expired |
| US6188627A | Method and system for improving DRAM subsystem performance using burst refresh control | Physics | 6 | Expired |
| US7409558B2 | Low-latency data decryption interface | Electricity | 4 | Active |
| US6836831B2 | Independent sequencers in a DRAM control structure | Physics | 4 | Expired |
| US10423550B2 | Managing efficient selection of a particular processor thread for handling an interrupt | Physics | 4 | Active |
| US6684279B1 | Method, apparatus, and computer program product for controlling data transfer | Physics | 3 | Expired |
| US10552351B2 | Techniques for issuing interrupts in a data processing system with multiple scopes | Physics | 3 | Active |
| US8069353B2 | Low-latency data decryption interface | Electricity | 2 | Active |
| US6523080B1 | Shared bus non-sequential data ordering method and apparatus | Physics | 1 | Expired |
| US7275125B2 | Pipeline bit handling circuit and method for a bus bridge | Physics | 1 | Expired |
| US7469312B2 | Computer system bus bridge | Physics | 1 | Active |
| US6185646A | Method and apparatus for transferring data on a synchronous multi-drop | Physics | 1 | Expired |
| US5748919A | Shared bus non-sequential data ordering method and apparatus | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.