Method for submicron gap filling on a semiconductor substrate
US6191026A · kind A · utility
117Cited by
18References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1996 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Jan 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.