Electrically programmable memory cell array, using charge carrier traps and insulation trenches

US6191459A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Hofmann · Munich, DE
• Wolfgang Krautschneider · Ottobrunn, DE
• Josef Willer · Riemerling, DE
• Hans Reisinger · Grünwald, DE

Key dates

• Filing date: Jan 8, 1997
• Grant date: Feb 20, 2001
• Expiry date: Jan 8, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/69

Abstract

An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F.sup.2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.