Fabrication method for gate spacer
US6194279A · kind A · utility
17Cited by
4References
22Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method for a gate spacer. The method comprises provision of a substrate with a gate formed thereon, after which a SiN.sub.x spacer is formed on the gate sidewall. The substrate is then covered with a SiO.sub.x layer. A part of the SiO.sub.x layer is removed until the surface of the SiO.sub.x layer is lower than the top surface of the gate. A portion of the SiN.sub.x layer is removed to expose the top edge of the gate spacer and to increase the exposed area of the gate. The SiO.sub.x layer is consequently removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.