High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers
US6194283A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1997 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Oct 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.