Method of fabricating an integrated circuit of logic and memory using damascene gate structure
US6194301A · kind A · utility
42Cited by
19References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jul 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.