Method of fabricating a narrow bit line structure
US6197630A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a narrow bit line structure is disclosed. The fabrication includes the steps as follows. At first, the interpoly dielectric layer is formed over the MOSFET. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer, the tungsten silicide layer, the silicon-oxy-nitride layer, and the second polysilicon layer is continuously formed over the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall. The silicon oxide layer is deposited over the second polysilicon layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer. The second polysilicon layer, the polysilicon spacer, a portion of the silicon-oxy-nitride layer, a portion of the tungsten silicide layer, and a portion of the first polysilicon layer is Sequentially etched to expose the interpoly dielectric layer, using the silicon oxide layer as a hard mask. Afte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.