Methods of forming thin film transistors
US6200839A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Jul 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.