Method for producing PMOS devices
US6200840A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Jun 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes a semiconductor substrate which is provided and forms a gate oxide layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, pattern transfers onto the photoresist layer after going through an exposure and a development. Furthermore, the gate layer and the gate oxide layer are then etched by using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin nitride oxide (NO, N.sub.2 O) layer is grown by utilizing rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN). Hereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A TEOS layer and a silicon nitride layer are deposited by using LPCVD, and forming spacers by etching the silicon nitride layer and the TEOS layer. Next, heavily doping of boron ions occurs as well as an annealing process. The final stage is a procedure of forming metal silicides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.