Processor-cache protocol using simple commands to implement a range of cache configurations
US6202125A · kind A · utility
60Cited by
42References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1997 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | May 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.