Method and system for pre-fetch cache interrogation using snoop port

US6202128A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kin Shing Chan · Austin, US
• Dwain A. Hicks · Pflugerville, US
• Peichun Peter Liu · Austin, US
• Michael John Mayfield · Austin, US
• Shih-Hsiung S. Tung · Austin, US

Key dates

• Filing date: Mar 11, 1998
• Grant date: Mar 13, 2001
• Expiry date: Mar 11, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/1054
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not. The snoop read access uses a (33-bit) real address to access the data cache without occupying a data port during …