Integrated circuit tester having pattern generator controlled data bus
US6202186A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Jan 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.