Process to make complementary silicide metal gates for CMOS technology
US6204103A · kind A · utility
43Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1998 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Sep 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.