Removal of silicon oxynitride on a capacitor electrode for selective hemispherical grain growth
US6204117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jul 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H.sub.3 PO.sub.4) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H.sub.3 PO.sub.4 wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.